1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly, it relates to a semiconductor device which is reduced in resistance by a salicide structure and a method of fabricating the same.
2. Description of the Background Art
In recent years, LSIs are refined due to the development of designs of integrated circuits and process techniques to enable fabrication of high-density integrated circuits, while high-speed operations are strongly required particularly in logic circuits. Reduction of resistance is effective means for attaining a high-speed operation, and reduction of contact resistance is attained by a salicide (self-aligned silicide) structure provided with low-resistance layers on contact parts of a source/drain and a gate electrode.
FIG. 55 is a sectional view of an element showing a conventional semiconductor device of a salicide structure. A p well 103 is formed on a surface of a semiconductor substrate 101. A field oxide film 102 is formed on an isolation region of the semiconductor substrate 101, so that a MOS (metal oxide semiconductor) transistor is formed in an active region which is enclosed with the field oxide film 102.
This MOS transistor has a pair of n-type extension layers 109, a pair of sources/drains 1010, a gate insulator film 106, and a gate electrode 107. The pair of n-type extension layers 109 are formed on the surface of the semiconductor substrate 101 at a prescribed distance, and the sources/drains 1010 are also formed on the surface of the semiconductor substrate 101 to be adjacent to the n-type extension layers 109. The n-type extension layers 109 and the sources/drains 1010 form an LDD (lightly doped drain) structure. The gate electrode 107 is formed on a region held between the pair of n-type extension layers 109 through the gate insulator film 106, and side surfaces of the gate electrode 107 are covered with side walls 108.
Metal silicide layers 1011 are formed on the gate electrode 107 and the sources/drains 1010, to be in contact therewith respectively.
A channel cut injection layer 104 is formed to be in contact with the lower surface of the field oxide film 102 in the isolation region and positioned at a prescribed depth from the surface of the semiconductor substrate 101 in the active region. Further, a channel injection layer 105 is formed in the active region on a shallower position than the channel cut injection layer 104.
An interlayer isolation film 1016 is formed to cover the MOS transistor, and provided with contact holes reaching the metal silicide layers 1011. Contacts 1017 are formed to fill up the contact holes.
As shown in FIG. 55, the metal silicide layers 1011 are formed between the contacts 1017 and the sources/drains 1010, thereby reducing the resistance. The metal silicide layers 1011 may be prepared from a metal such as Co, Ni, Ti, W or Pt.
In the conventional semiconductor device, however, it is so difficult to completely;control the shape of each metal silicide layer 1011 that the same may extend into a portion under the field oxide film 102 along the boundary between the field oxide film 102 and each source/drain 1010, as shown in FIG. 56. This phenomenon remarkably takes place particularly when the metal silicide layer 1011 is prepared from a metal such as Co or Ni serving as a diffusion species when reacting with silicon.
Thus, the distance between a pn junction formed by each source/drain 1010 and the p well 103 and an end portion of the metal silicide layer 1011 may be reduced, or the metal silicide layer 1011 may project beyond the source/drain 1010, to result in direct connection between the metal silicide layer 1011 and the p well 103, the channel cut injection layer 104 or the channel injection layer 105 formed in the semiconductor substrate 101.
When a metal film is formed after formation of an isolation insulator film, an end portion of the field oxide film 102 may be eroded by wet etching performed before formation of the metal film for removing a natural oxide film, as shown in FIG. 57.
When the end portion of the field oxide film 102 is eroded, a surface part of the semiconductor substrate 101 may be exposed on this portion, to result in direct connection between each metal silicide layer 1011 and the p well 103, the channel cut injection layer 104 or the channel injection layer 105 formed in the semiconductor substrate 101, or reduction of: the distance between the pn junction formed by each source/drain 101 and the p well 103 and the end portion of the metal silicide layer 1011.
Also when trench isolation is employed, a metal silicide layer 1011 may extend into a portion under an end portion of a buried oxide film 1018 as shown in FIG. 58 or the end portion of the buried oxide film 1018 may be eroded as shown in FIG. 59, if the metal silicide layer 1011 is prepared from Co or Ni. Thus, the distance between a pn junction formed by a source/drain 1010 and a p well 103 and an end portion of the metal silicide layer 1011 may be reduced or the metal suicide layer 1011 may project beyond the source/drain 1010, to result in direct connection between the metal silicide layer 1011 and the p well 103, a channel cut injection layer 104 or a channel injection layer 105 formed in the semiconductor substrate 101.
If the metal silicide layer 1011 projects beyond the source/drain 1010 to be directly connected with the p well 103, the channel cut injection layer 104 or the channel injection layer 105, a leakage current flows between the source/drain 1010 and the p well 103 upon application of a voltage, to extremely reduce the reliability of the element.
Also when the distance between the pn junction formed by the source/drain 1010 and the p well 103 and the metal silicide layer 1011 is reduced a depletion layer grows due to voltage application, and hence the metal silicide layer 1011 is disadvantageously electrically connected with the p well 103 to increase the leakage current and reduce the reliability of the element.
To this end, low-concentration n-type impurity layers 1091 are formed to attain reduction of the leakage current, as shown in FIG. 60. This technique is disclosed in U.S. Pat. No. 4,949,136, for example.
In such a structure, however, punch-through disadvantageously takes place if the low-concentration n-type impurity layers 1091 are deeply formed for preventing projection of metal silicide layers 1011 on end portions of a field oxide film 102.
In this structure, further, punch-through readily takes place if side walls 108 and 1081 are reduced in thickness. If the side walls 108 and 1081 are increased in thickness, on the other hand, exposed surface parts of sources/drains 1010 are so reduced that the resistance is disadvantageously increased due to insufficient contact.
An object of the present invention is to provide a semiconductor device which can reduce a junction leakage current while maintaining a sufficient contact width without increasing the depth of a source/drain, for attaining a high-speed operation with no deterioration of its element characteristics following refinement, and a method of fabricating the same.
A semiconductor device according to the present invention comprises a first conductivity type semiconductor substrate, an isolation insulator film which is formed on an isolation region of a major surface of the semiconductor substrate, a second conductivity type source and a second conductivity type drain which are formed at
an active region enclosed with the isolation region on the major surface of the semiconductor substrate, a gate electrode which is formed on a major surface of the active region through a gate insulator film, metal compound layers which are formed on surfaces of the source, the drain and the gate electrode respectively, and second conductivity type first impurity layers which are formed on boundary portions between the source and the drain and the isolation region to be deeper than the source and the drain.
The inventive semiconductor device having the aforementioned structure attains the following effect:
Each first impurity layer of the same conductivity type as the source/drain is formed on the boundary portion between the source/drain and the field oxide film in a portion deeper than the source/drain in the semiconductor device according to the present invention, whereby the semiconductor substrate is connected with no metal compound layer even if any metal compound layer extends into a portion under the isolation insulator film or an end portion of the isolation insulator film is eroded, and the reliability of the element operation is improved such that a leakage current is suppressed while maintaining the depth of the source/drain.
In the aforementioned aspect, the semiconductor device preferably further comprises a first conductivity type second impurity layer having an impurity concentration peak, which is formed to be deeper than the first impurity layers and to be in contact with the bottom surface of the isolation insulator film.
The second impurity layer of the same conductivity type as the semiconductor substrate is formed to be in contact with the bottom surface of the isolation insulator film, whereby formation of a parasitic transistor can be prevented.
In the aforementioned aspect, the second impurity layer is preferably formed only under the isolation insulator film.
The second impurity layer is formed only under the isolation insulator film, whereby the area of the second impurity layer is reduced to reduce the junction capacity to attain a high-speed operation, while the second impurity layer is prevented from influencing a threshold voltage, whereby the reliability of the element is further improved.
In the aforementioned aspect, the semiconductor device preferably further comprises side wall insulator films which are formed on side: surfaces of the gate electrode, a pair of second conductivity type third impurity layers which are formed under the respective side wall insulator films at the major surface of the active region to be shallower than the source and the drain, and first conductivity type fourth impurity layers which are formed to enclose the third impurity layers respectively.
The first conductivity type fourth impurity layers are formed to enclose the second conductivity type third impurity layers, whereby punch-through is suppressed, increase of the junction capacity and the junction leakage current is also suppressed and a load is reduced, to enable a high-speed circuit operation.
In the aforementioned aspect, the isolation insulator film is at least either a field oxide film or a buried oxide film filling up a trench provided at the major surface of the semiconductor substrate, and the metal compound layers are Co silicide layers.
The impurity layer of the same conductivity type as the source/drain is formed on the boundary portion between the source/drain and the isolation insulator film in a portion deeper than the source/drain, whereby the semiconductor substrate is connected with no metal silicide layer even if any metal silicide layer such as a Co silicide layer or an Ni silicide layer extends into a portion under the field oxide film or the buried oxide film, and the reliability of the element operation is improved such that the leakage current is suppressed while maintaining the depth of the source/drain.
In the aforementioned aspect, it is preferable that the second conductivity type is an n type, the first conductivity type is a p type, the source/drain and the third impurity layers are made of arsenic, and the first impurity layers are made of phosphorus.
The leakage current is further suppressed since n-type impurity layers are deeply formed with phosphorus which is easy to diffuse, while punch-through is suppressed since the source/drain and an n-type extension layer are shallowly formed with arsenic which is hard to diffuse.
According to another aspect of the present invention, a method of fabricating a semiconductor device comprises steps of forming an isolation insulator film on an isolation region of a major surface of a first conductivity type semiconductor substrate, forming a gate electrode on a major surface of an active region enclosed with the insolation region through a gate insulator film, forming a source and a drain at the major surface of the semiconductor substrate, epitaxially growing silicon layers on surfaces of the gate electrode, the source and the drain, forming first impurity layers on boundary portions between the source and the drain and the isolation region to be deeper than the source and the drain by injecting a second impurity, and forming metal compound layers on the surfaces of the gate electrode, the source and the drain.
The first impurity layers are formed under end portions of the isolation insulator film in a self-aligned manner by the silicon layers formed on the surfaces of the gate electrode and the source/drain in a self-aligned manner and the isolation insulator film having a large thickness on a central portion and a small thickness on the end portions. Thus, it is possible to obtain a method of fabricating a semiconductor device which is improved in reliability of its element operation through simplified steps.
In the aforementioned aspect, the method preferably further comprises a step of forming a second impurity layer having an impurity concentration peak to be deeper than the first impurity layers and to be in contact with the bottom surface of the isolation insulator film by injecting a first conductivity type impurity into the overall surface.
The second impurity layer, of the same conductivity type as the semiconductor substrate is formed in a self-aligned manner to be in contact with the bottom surface of the isolation insulator film. Thus, it is possible to obtain a method of fabricating a semiconductor device suppressing formation of a parasitic transistor through simplified steps.
In the aforementioned aspect, the step of forming the isolation insulator film preferably includes steps of forming a trench at the major surface of the semiconductor substrate through a mask of a silicon nitride film, forming an insulator film on the overall surface to fill up the trench, and etching back the insulator film and the silicon nitride film, and the method preferably further comprises a step of forming a second impurity layer having an impurity concentration peak on the bottom surface of the trench by injecting a first conductivity type impurity following the step of forming the trench.
Thus, the area of the second impurity layer is reduced to reduce the junction capacity, whereby it is possible to obtain a method of fabricating a semiconductor device which can attain a high-speed operation. In addition, the second impurity layer is prevented from influencing a threshold voltage, whereby it is possible to obtain a method of fabricating a semiconductor device which is further improved in element reliability.
In the aforementioned aspect, the method preferably further comprises steps of forming a pair of second impurity layers at the major surface of the semiconductor substrate at a prescribed space by injecting a second conductivity type impurity into the overall surface after forming the gate electrode, forming first conductivity type third impurity layers to enclose the second impurity layers respectively, forming side walls on side surfaces of the gate electrode, and forming a source and a drain to be deeper than the second impurity layers by injecting a second conductivity type impurity into the overall surface.
The first conductivity type third impurity layers are formed to enclose the second conductivity type second impurity layers, whereby punch-through is suppressed, increase of the junction capacity and the junction leakage current is suppressed and the load is reduced. Thus, it is possible to obtain a method of fabricating a semiconductor device enabling a high-speed circuit operation.
According to still another aspect of the present invention, a method of fabricating a semiconductor device comprises steps of forming a silicon nitride film on an active region of a major surface of a first conductivity type semiconductor substrate, forming an isolation insulator film on an isolation region through the silicon nitride film serving as a mask, forming a gate electrode on the major surface of the semiconductor substrate through a gate insulator film by etching a gate electrode forming region of the silicon nitride film, forming second conductivity type first impurity layers by injecting a second conductivity type impurity, removing the silicon nitride film, forming a source and a drain at the major surface of the semiconductor substrate, and forming metal compound layers on surfaces of the gate electrode and the source and the drain, and the first impurity layers are formed on boundary portions between the source and the drain and the isolation region to be deeper than the source and the drain.
The first impurity layers are formed under end portions of the isolation insulator film in a self-aligned manner by the silicon nitride film formed for forming the isolation insulator film, whereby it is possible to obtain a method of fabricating a semiconductor device which is improved in reliability of its element operation through simplified steps.
In the aforementioned aspect, the method preferably further comprises a step of forming a second impurity layer having an impurity concentration peak to be deeper than the first impurity layers and to be in contact with the bottom surface of the isolation insulator film by injecting a first conductivity type impurity into the overall surface.
The second impurity layer of the same conductivity type as the semiconductor substrate is formed in a self-aligned manner to be in contact with the bottom surface of the isolation insulator film, whereby it is possible to obtain a method of fabricating a semiconductor device suppressing formation of a parasitic transistor through simplified steps.
In the aforementioned aspect, the step of forming the isolation insulator film preferably has steps of forming a trench at the major surface of the semiconductor substrate through the silicon nitride film serving as a mask, forming an insulator film on the overall surface to fill up the trench, and etching back the insulator film and the silicon nitride film, and the method preferably further comprises a step of forming a second impurity layer having an impurity concentration peak at the bottom surface of the trench by injecting a first conductivity type impurity following the step of forming the trench.
Thus, the area of the second impurity layer is reduced to reduce the junction capacity and it is possible to obtain a method of fabricating a semiconductor device which can attain a high-speed operation. In addition, the second impurity layer is prevented from influencing a threshold voltage, whereby it is possible to obtain a method of fabricating a semiconductor device further improved in element reliability.
In the aforementioned aspect, the method preferably further comprises steps of forming a pair of second impurity layers at the major surface of the semiconductor substrate at a prescribed space by injecting a second conductivity type impurity into the overall surface after forming the gate electrode, forming first conductivity type third impurity layers to enclose the second impurity layers respectively, forming side walls on side surfaces of the gate electrode, and forming a source and a drain to be deeper than the second impurity layers by injecting a second conductivity type impurity into the overall surface.
The first conductivity type third impurity layers are formed to enclose the second conductivity type second impurity layers, whereby punch-through is suppressed, increase of the junction capacity and the junction leakage current is suppressed and the load is reduced, and it is possible to obtain a method of fabricating a semiconductor device enabling a high-speed circuit operation.
In the aforementioned aspect, the method preferably further comprises a step of forming a second impurity layer having an impurity concentration peak by etching the gate electrode forming region of the silicon nitride film and injecting a first conductivity type impurity into the overall surface.
A channel injection layer is formed not under the source/drain but only under the gate electrode in a self-aligned manner, whereby increase of the junction capacity and the junction leakage current is suppressed and the load is reduced, to enable a high-speed circuit operation.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.